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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd23c128000bl 128m-bit mask-programmable rom 16m-word by 8-bit (byte mode) / 8m-word by 16-bit (word mode) data sheet document no. m15900ej3v0ds00 (3rd edition) date published february 2003 ns cp (k) printed in japan the mark shows major revised points. 2002 description the pd23c128000bl is a 134,217,728 bits mask-programmable rom. the word organization is selectable (byte mode : 16,777,216 words by 8 bits, word mode : 8,388,608 words by 16 bits). with 44-pin plastic sop package products, only word mode can be used; it is not possible to switch to byte mode. the active levels of oe (output enable input) can be selected with mask-option. the pd23c128000bl is packed in 48-pin plastic tsop (i) and 44-pin plastic sop. features ? word organization 16,777,216 words by 8 bits (byte mode) note 8,388,608 words by 16 bits (word mode) note note with 44-pin plastic sop package products, only word mode can be used. it is not possible to switch to byte mode. ? operating supply voltage : v cc = 2.7 to 3.6 v operating supply voltage access time power supply current (active mode) standby current (cmos level input) v cc ns (max.) ma (max.) a (max.) 3.0 v 0.3 v 120 50 30 3.3 v 0.3 v 100 55 ordering information part number package pd23c128000blgy- xxx-mjh 48-pin plastic tsop(i) (12x18) (normal bent) pd23c128000blgy- xxx-mkh 48-pin plastic tsop(i) (12x18) (reverse bent) pd23c128000blgx-xxx 44-pin plastic sop (15.24 mm (600)) (xxx : rom c ode suffix no.)
data sheet m15900ej3v0ds 2 pd23c128000bl pin configurations /xxx indicates active low si gnal. 48-pin plastic tsop (i) (12x18) (normal bent) [ pd23c128000blgy-xxx-mjh ] marking side word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a ? 1 o7 o14 o6 o13 o5 o12 o4 v cc v cc a22 o11 o3 o10 o2 o9 o1 o8 o0 /oe or oe or dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 to a22 : address inputs o0 to o7, o8 to o14 : data outputs o15, a?1 : data output 15 (word mode), lsb address input (byte mode) word, /byte : mode select input /ce : chip enable input /oe or oe : output enable input v cc : supply voltage gnd : ground dc : don?t care remark refer to package drawings for the 1-pin index mark.
data sheet m15900ej3v0ds 3 pd23c128000bl 48-pin plastic tsop (i) (12x18) (reverse bent) [ pd23c128000blgy-xxx-mkh ] marking side word, /byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 a21 a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd gnd o15, a ? 1 o7 o14 o6 o13 o5 o12 o4 v cc v cc a22 o11 o3 o10 o2 o9 o1 o8 o0 /oe or oe or dc gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 to a22 : address inputs o0 to o7, o8 to o14 : data outputs o15, a?1 : data output 15 (word mode), lsb address input (byte mode) word, /byte : mode select input /ce : chip enable input /oe or oe : output enable input v cc : supply voltage gnd : ground dc : don?t care remark refer to package drawings for the 1-pin index mark.
data sheet m15900ej3v0ds 4 pd23c128000bl 44-pin plastic sop (15.24 mm (600)) [ pd23c128000blgx-xxx ] marking side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a21 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 /ce gnd /oe or oe or dc o0 o8 o1 o9 o2 o10 o3 o11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a20 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 a22 gnd o15 o7 o14 o6 o13 o5 o12 o4 v cc a0 to a22 : address inputs o0 to o15 : data outputs /ce : chip enable /oe or oe : output enable v cc : supply voltage gnd : ground dc : don?t care remarks 1. refer to package drawings for the 1-pin index mark. 2. with 44-pin plastic sop package products, only word mode (8,388,608 words x 16 bits) can be used. there is no mode select (word, /byte) pin.
data sheet m15900ej3v0ds 5 pd23c128000bl input / output pin functions pin name input / output function word, /byte input the pin for switching word mode and byte mode. high level : word mode (8m-word by 16-bit) low level : byte mode (16m-word by 8-bit) a0 to a22 (address inputs) input address input pins. a0 to a22 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) a0 to a22 are used as 23 bits address signals. byte mode (16m-word by 8-bit) a0 to a22 are used as the upper 23 bits of total 24 bits of address signal. (the least significant bit (a ? 1) is combined to o15.) o0 to o7, o8 to o14 (data outputs) output data output pins. o0 to o7, o8 to o14 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) the lower 15 bits of 16 bits data outputs to o0 to o14. (the most significant bit (o15) combined to a ? 1.) byte mode (16m-word by 8-bit) 8 bits data outputs to o0 to o7 and also o8 to o14 are high impedance. o15, a ? 1 (data output 15, lsb address input) output, input o15, a ? 1 are used differently in the word mode and the byte mode. word mode (8m-word by 16-bit) the most significant output data bus (o15). byte mode (16m-word by 8-bit) the least significant address bus (a ? 1). /ce (chip enable) input chip activating signal. when the oe is active, output states are following. high level : high-z low level : data out /oe or oe or dc (output enable, don?t care) input output enable signal. the active level of oe is mask option. the active level of oe can be selected from high active, low active and don?t care at order. v cc ? supply voltage gnd ? ground
data sheet m15900ej3v0ds 6 pd23c128000bl block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 o15, a ? 1 word, /byte /oe or oe or dc /ce output buffer y-selector memory cell matrix 8,388,608 words by 16 bits / 16,777,216 words by 8 bits address input buffer x-decoder logic/input input buffer y-decoder a19 o14 o13 o12 o11 o10 o9 o8 o0 o1 o2 o3 o4 o5 o6 o7 a20 a21 a22
data sheet m15900ej3v0ds 7 pd23c128000bl mask option the active levels of output enable pin (/oe or oe or dc) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. option /oe or oe or dc oe active level 0/oe l 1oe h x dc don?t care operation modes for each option are shown in the tables below. operation mode (option : 0) /ce /oe mode output state l l active data out h high-z h h or l standby high-z operation mode (option : 1) /ce oe mode output state l l active high-z h data out h h or l standby high-z operation mode (option : x) /ce dc mode output state l h or l active data out h h or l standby high-z remark l : low level input h : high level input
data sheet m15900ej3v0ds 8 pd23c128000bl electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.3 to +4.6 v input voltage v i ?0.3 to v cc +0.3 v output voltage v o ?0.3 to v cc +0.3 v operating ambient temperature t a ?10 to +70 c storage temperature t stg ?65 to +150 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (t a = 25 c) parameter symbol test condition min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o 12 pf dc characteristics (t a = ?10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test conditions min. typ. max. unit high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il v cc = 3.0 v 0.3 v ?0.3 +0.5 v v cc = 3.3 v 0.3 v ?0.3 +0.8 high level output voltage v oh i oh = ?100 a2.4v low level output voltage v ol i ol = 2.1 ma 0.4 v input leakage current i li v i = 0 v to v cc ?10 +10 a output leakage current i lo v o = 0 v to v cc , chip deselected ?10 +10 a power supply current i cc1 /ce = v il (active mode), v cc = 3.0 v 0.3 v 50 ma i o = 0 ma v cc = 3.3 v 0.3 v 55 standby current i cc3 /ce = v cc ? 0.2 v (standby mode) 30 a
data sheet m15900ej3v0ds 9 pd23c128000bl ac characteristics (t a = ?10 to +70 c, v cc = 2.7 to 3.6 v) parameter symbol test condition v cc = 3.0 v 0.3 v v cc = 3.3 v 0.3 v unit min typ. max. min typ. max. address access time t acc 120 100 ns address skew time t skew note 10 10 ns chip enable access time t ce 120 100 ns output enable access time t oe 25 25 ns output hold time t oh 00ns output disable time t df 0 20 0 20 ns word, /byte access time t wb 120 100 ns note t skew indicates the following three types of time depending on the condition. 1) when switching /ce from high level to low level, t skew is the time from the /ce low level input point until the next address is determined. 2) when switching /ce from low level to high level, t skew is the time from the address change start point to the /ce high level input point. 3) when /ce is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /ce is active, t skew is not subject to limitations when /ce is switched from high level to low level following address determination, or when the address is changed after /ce is switched from low level to high level. remark t df is the time from inactivation of chip enable input (/ce) or output enable input (/oe or oe) to high impedance state output. ac test conditions input waveform (rise / fall time 5 ns) test points 1.4 v 1.4 v output waveform test points 1.4 v 1.4 v output load 1ttl + 100 pf
data sheet m15900ej3v0ds 10 pd23c128000bl cautions on power application to ensure normal operation, always apply power using /ce following the procedure shown below. 1) input a high level to /ce during and after power application. 2) hold the high level input to /ce for 200 ns or longer (wait time). 3) start normal operation after the wait time has elapsed. power application timing chart 1 (when /ce is made high at power application) wait time 200 ns or longer normal operation /ce (input) v cc power application timing chart 2 (when /ce is made high after power application) wait time 200 ns or longer normal operation /ce (input) v cc caution other signals can be either high or low during the wait time.
data sheet m15900ej3v0ds 11 pd23c128000bl read cycle timing chart t acc t oh t ce t oe t skew t skew t skew t oh t oh t df note2 t df note2 t acc t acc data out data out data out (input) (input) (input) (input) a0 to a22, a ? 1 note1 o0 to o7, o8 to o15 note3 /ce /oe or oe high-z high-z notes 1. during word mode, a?1 is o15. 2. t df is the time from inactivation of chip enable input (/ce) or output enable input (/oe or oe) to high impedance state output. 3. during byte mode, o8 to o14 are high impedance and o15 is a?1. word, /byte switch timing chart data out a ? 1 (input) word, /byte (input) high-z high-z data out data out high-z o0 to o7 (output) o8 to o15 (output) t oh t acc t oh t wb data out data out t df remark chip enable (/ce) and output enable (/oe or oe) : active.
data sheet m15900ej3v0ds 12 pd23c128000bl package drawings notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) r k l 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mjh1-1 s 0.60 0.15 j 0.8 0.2 s q s n e g f j detail of lead end c d m m b a i p 1 24 48 25 s
data sheet m15900ej3v0ds 13 pd23c128000bl 0.145 0.05 notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) c b r k d m m 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mkh1-1 s 0.60 0.15 j 0.8 0.2 s n j g f l s q e detail of lead end 1 24 48 25 s a i p
data sheet m15900ej3v0ds 14 pd23c128000bl 44-pin plastic sop (15.24 mm (600)) note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. item millimeters c 0.78 max. b 1.27 (t.p.) e 0.15 0.1 f 3.0 max. g 2.7 0.05 h 16.04 0.3 i 13.24 0.1 j 1.4 0.2 m 0.12 n 0.10 l 0.8 0.2 k 0.22 + 0.08 ? 0.07 p3 + 7 ? 3 d 0.42 + 0.08 ? 0.07 a 27.83 + 0.4 ? 0.05 p44gx-50-600a-4 k l g p dm b j detail of lead end s n m f e c 44 23 122 s h i a
data sheet m15900ej3v0ds 15 pd23c128000bl recommended soldering conditions please consult with our sales offices for soldering conditions of the pd23c128000bl. types of surface mount device pd23c128000blgy- xxx-mjh : 48-pin plastic tsop(i) (12x18) (normal bent) pd23c128000blgy- xxx-mkh : 48-pin plastic tsop(i) (12x18) (reverse bent) pd23c128000blgx-xxx : 44-pin plastic sop (15.24 mm (600))
data sheet m15900ej3v0ds 16 pd23c128000bl revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 3rd edition/ p.9 p.9 addition ac characteristics address skew time (t skew ) feb. 2003 note p.10 ? addition cautions on power application p.11 p.10 modification read cycle timing chart
data sheet m15900ej3v0ds 17 pd23c128000bl [memo]
data sheet m15900ej3v0ds 18 pd23c128000bl [memo]
data sheet m15900ej3v0ds 19 pd23c128000bl notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 note: 3 status before initialization of mos devices handling of the applied waveform of input pins and the unused input pins for cmos note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. input levels of cmos devices must be fixed. cmos devices behave differently than bipolar or nmos devices. if the input of a cmos device stays in an area that is between v il (max.) and v ih (min.) due to the effects of noise or some other irregularity, malfunction may result. therefore, not only the input waveform is fixed, but also the waveform changes, it is important to use the cmos device under ac test conditions. for unused input pins in particular, cmos devices should not be operated in a state where nothing is connected, so input levels of cmos devices must be fixed to high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices.
pd23c128000bl these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of february, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec el ectronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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